Digital-to-time converter (DTC) based fractional-N phase lock loops (PLLs) have demonstrated low power consumption, low phase noise, and good figures-of-merit compared to other fractional-N PLL architectures. DTC-based fractional-N PLLs can be realized in both digital PLL form and analog PLL form.
In-band phase noise of PLLs can be improved by doubling the reference clock rate. However, the reference clock does not typically have a 50% duty cycle, and doubling the reference clock may cause duty cycle errors which need to be corrected.